Plasma display system

ABSTRACT

Visual display systems such as plasma displays in which a diode and resistor matrix provides writing, erasing and sustaining voltages to a plurality of elemental areas to produce visual indications without interference between the various supplied voltages, whether dc, ac or pulse for coupling control signals and logic to a large number of elements with a reduction in the required number of switches and circuit connections is described.

United States Patent [191 1111 3,754,230 Auger 1 Aug. 21, 1973 PLASMADISPLAY SYSTEM 3,573,542 4/1971 Mayer et a1 340/324 R 2,995,682 8/1961Livingston 315/169 R [75] Invent Ernes Auger Blnenca, Mass- 3,609,7469/1971 Trogdon 340/324 R [73] Assignee: Raytheon Company, Lexington,

M Primary ExaminerDavid L. Trafton Attorney-Milton D. Bartlett, JosephD. Pannone, [22] Filed: 1970 Herbert W. Arnold and David M. Warren [21]Appl. No.: 99,798

[57] ABSTRACT 52 us. c1. 340/324 M, 315/169 R, 315/171, Visual p ysystems such as plasma p y in which 340/1 EL a diode and resistor matrixprovides writing, erasing [51] Int. Cl. G08b 5/36 and Sustainingvoltages a plurality of elemental areas [58] Field of Search 340/324 R,166 EL; to produce visual indications i h u int rferen e be 315/1 9 R171 tween the various supplied voltages, whether dc, ac or pulse forcoupling control signals and logic to a large 5 R f r Cited number ofelements with a reduction in the required number of Switches and Circuitconnections is de- 3,689,912 9/1972 Dick 340/324 R scnbed' 3,559,1901/1971 Bitzer et a1. 340/173 18 Claims, 16 Drawing Figures WRITE ERASERESET SUSTAIN 1 -//6 SUSTAINER lWRlTE/ERASE GENERATOR M0 DRIVER 5 1NEGATIVE R EDGE *1 I S W l T C H 8311a,, i D L l L -I l an ----1 I i//30 //34 l 1 m4 m6 /0& //0 A ./B X AXIS PA N E L L! N E s 1 l //203%r/24 -/28 -52 T 1;; 1 A l f /46 F /48 1 1 M N 3 5 &1 .43 1 I00 SUSTAINg E SWITCH 1 i e V/2A Shaw 25 PArEmEumm ms SHEET 1 (IF 7 l8 /0 I) ISWITCHING UTILIZATION CENTRAL MATRIX DEVICE COMPUTER SWITCHINGUTILIZATION MATRIX DEVICE W, $WITCHING UTILIZATION MATRIX DEVICE WRITEERASE RESET SUSTAIN I //4 WRlTE/ERASE G E I I E R A TDTQ M0 DRIVER IPAIENTEIIIIIIIm Ian 3,754,230

SHEU UT 7 /68 /76 TO FROM TO FROM IsOLATION susTAINER IsOLATIONwRITE/ERAsE N ETWQRK GENERATOR NETWORK DRIVER FROM FROM LOGIc LOGIcMATRIX MATRIX [-76 /2 -92 LOGIC 76 84 susTAIN SWITCHES 88 WR'TEIERASE IsusTAINER DR'VER GENERATOR I I6 l ,wRITE/ERAsE LINES SWITCHES l6 70 73LINES l ISOLATION V LOGIC "94 NETWORK 25s 74 LINES g x CHANNEL GENTRALPLASMA COMPUTER DISPLAY Y HANNEL 256 I0 96 LINEs i V LOGIc ISOLATIONNETWORK a0 LIISES 86. v susTAI N I6 I SWITCHES LNES WRITE/ERASE SUSTAINER DR'VER GENERATOP 90 WRITE/ERASE SWITCHES V LOGIC PATENTEUMJBZI maSHEET 5 OF 7 WQY W w l I l 4 1 1 w fi l fiw u E PATENIEDAUSZI I975 SHEET7 [IF 7 FROM Y 386 W/E SWITCH 350 380/ -FROM Y-SUSTAINER SWITCH JFROM wE SWITCH FROM Y-SUSTAINER SWITCH FROM X r SUSTAINER SWITCH FROM X W/ESWITCH FROM X SUSTAINER SWITCH FROM x W/E SWITCH PLASMA DISPLAY SYSTEMBACKGROUND AND SUMMARY OF THE INVENTION This invention relates to visualdisplay systems having a switching and control matrix providing for thesimplification of circuitry and the reduction of components forswitching and control of a large quantity of input signals. Moreparticularly, a visual display system is described embodying the presentinvention in which a display is provided by a matrix which is animprovement over prior art systems in that fewer components and circuitconnections are required to couple data from a computer or other datainput source to the display. Isolation of the power signals, required toprovide the major portion of the visual indication energy and/or tosustain display data from data signals, required to write or erase data,is provided by circuitry which allows the data signals to be appliedsimultaneously with the power signals without loss of data. Prior artsystems cannot apply these voltages simultaneously because such systemscannot provide for isolation, and, in systems of the prior art, loss ofdata and fading can occur when writing or erasing, thus, an improveddisplay system requiring fewer components and circuit connections with aresultant savings in cost is provided.

The present invention provides a method of applying an alternating orvarying dc voltage to a plurality of nodes of a matrix simultaneously,with the ability to increase the voltage or pulse on any single nodesimultaneously and without interference with the voltage on the othernodes. This technique is particularly applicable to those visualdisplays in which visual indications are controlled by linesindividually connected to each of said nodes and using circuitry inwhich two or more control signals or nodes are required to switch orgate a large number of incoming data signals through a matrix to thedisplay system.

Display systems of the prior art, in which control signals must bebrought to the display elements require in addition to circuitconnections in the X and Y plane for every element, a switching circuitfor each element to provide for element selection. In a display of 256by 256 elements, a minimum of 1,024 switches would be required. Thepresent invention optimally requires a number of switches substantiallyequal to twice the square root of the number of lines in each channel oraxis. Thus, for a 256 by 256 matrix, only 32 switches for the X axis andthirty-two switches for the Y axis, for a total of 64 switches arerequired to gate in all of the memory control signals.

If a writing signal were inadvertently superimposed upon a power orsustaining signal, the wrong element would light and an inaccurate andincoherent display would result. This is the reason that systems of theprior art required individual switches for individual elements toprovide isolation.

The present invention provides a plurality of switches for the X and Yaxis of the crossed grids of a capacitively coupled display in which theswitches are used only when the displayed data is to be changed. Thedata that is not changed is displayed by the continued application of asustaining voltage through the switches which are all open and consumingno power.

In voltage controlled displays such as a plasma display, a gas dischargemay be maintained or sustained by a voltage less than that required tocreate the discharge, hence, the plasma display has an inherent memoryin the sense that as long as a sustainer voltage is applied to thedisplay, the displayed data, which is comprised of a plurality ofglowing cells, will be maintained by the sustainer alone with norequirement that refresh signals be continuously supplied from a centraldata source such as a computer. Thus, computer interface time is greatlyminimized in a plasma display system. An additional advantage of such asystem is that the display and circuitry associated therewith isessentially flat, since no cathode ray tube is required, and because itis transparent, the plasma display may be used as an overlay overanother display source such as a cathode ray tube display to give acomposite display.

The circuitry of the present invention permits writing and erasingvoltages to be applied to selected crossings of X and Y axis grid pointsby closing selected Write/E- rase switches and opening selectedsustainer switches in accordance with predetermined logic. The closedswitches brings the desired voltages to nodes through isolation diodesand resistors, and the open switches prevents the voltages from beingshunted from the desired nodes to undesired nodes. All. of the closedswitches shunt other nodes to the sustaining voltage source. Writingspeed is increased in the present system because the sustainingvoltagedoes not have to be removed from any nodes when writing at other nodesas in the prior art, hence, simultaneous writing and sustaining isaccomplished by the present invention. The present system gates thedigital input signals to the switches which in turn gates the requiredcontrol voltages to the display.

BRIEF DESCRIPTION OF THE DRAWINGS Other and further advantages of theinvention will become apparent in connection with the accompanyingdrawings wherein:

FIG. 1 illustrates a block diagram of a system embodying the invention;

FIG. 2 illustrates a plasma display panel of the type with which thepresent invention may be utilized;

FIG. 3 illustrates a gas discharge characteristic curve;

FIGS. 4 through 7 illustrate functional equivalent circuits of thevarious operating modes of an embodiment of the present invention; I

FIG. 8 is a waveform employed in an" embodiment of the presentinvention;

FIG. 9 is a block diagram of an embodiment of the present invention;

FIG. 10 is a simplified equivalent circuit diagram of an embodiment ofthe present invention;

FIG. 11 is a circuit diagram of a sustainer switch of the presentinvention;

FIG. 12 is a circuit diagram of a write and erase switch of the presentinvention;

FIG. 13 is a circuit diagram of a sustainer generator for generating thewaveform of FIG. 8 in accordance with the present invention;

FIG. 14 is a circuit diagram of a driver circuit in accordance with thepresent invention;

FIG. 15 is a circuit diagram of the X axis circuit connection to a 64line plasma display; and

FIG. 16 is a circuit diagram of the X and Y axis circuit connection to afour line plasma display.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, aswitching matrix in accordance with the present invention is illustratedcoupled to a central computer shown generally at 10. Positional data,radar presentations, weather data and other information is stored orreceived at computer for coupling to and display or storage atutilization devices such as 18, and 22 which may comprise visualdisplays or other signal utilization means. Switching matrix 12 couplesdata from the computer 10 to utilization device 18 without the need forrefreshing signals from the computer, with minimal circuit connections,and with less demand on computer time than systems requiring a constantrefresh, due to the inherent memory of a plasma display in conjunctionwith reduced data requirements and reduced circuitry. Other utilizationdevices, particularly displays of the plasma type, may be coupled tocomputer 10 by additional switching matrixes 14 and 16, which serve tocouple different signals which may be dc or ac voltages or pulses to thedisplays simultaneously and without mutual interference.

Referring now to FIG. 2, there is illustrated a plasma display panel ofthe capacitive discharge type with which the present invention isparticularly advantageous. Essentially, the panel is a flat gas filledglass plate with orthogonal conductors which may be plated thereon onopposite sides of a glass plate. Glass plates 30 and 32 form a backingon horizontal and vertical rows of conductors 34 and 36 respectivelywith thin layers of glass 38 and 40 deposited between the conductors andthe plasma 42 such that a point of light appears at the junction of arow and a column connector when an appropriate voltage is applied to anypair of lines. A constant ac voltage, the sustainer, must be applied toall of the lines to sustain the light after the initial discharge orwriting, thus the panel has discreet threshholds for writing, erasing,and sustaining as will be explained.

The plasma display is a digital storage device with two stable statesdetermined by the presence or absence of charge on the glass plates 38and 40. The individual cells of the display are excited by analternating signal, the amplitude of which, when large enough, causesthe gas in the cell to ionize when the voltage exceeds the firingpotential of the plasma, which discharge develops into a glow andilluminates the transparent glass walls 30 and 32. The plasma displayaccepts digital data directly with no analog circuit requirements, andstores the data by virtue of its inherent memory" resulting from thewall charge on the display walls. The capacitive coupling to the plasmacells provides natural isolation, and since no electrodes are present inthe cell, higher density displays then are possible with conduction typeplasma displays may be realized.

Referring now to FIG. 3, there is shown a graph illustrating theoperation of a typical gas tube which generally corresponds to anindividual elemental area of a plasma display. The term minimumbreakdown distance" is defined as being the distance between twoelectrodes in a gaseous medium where the smallest voltage between theelectrodes is required to create a discharge between the electrodes. Itmay be noted that this distance will vary in accordance with thepressure and type of gas surrounding the electrodes and electrodeconfiguration. When the grid is positioned at the minimum breakdowndistance from the cathode, the oscillations produced in a gas tube priorto breakdown of the tube will be less than those produced with otherspacings of the electrodes since the oscillation generated between thegrid and cathode in general vary directly as a function of the voltageapplied between the grid and cathode. Thus, by positioning the grid atthe minimum breakdown distance from the cathode, maximum stability ofthe device is achieved.

The voltage between the grid and the cathode of a typical gas tube isplotted along the abscissa of the graph and the current drawn fromcathode to grid is plotted along the ordinate in amperes. When thecurrent of the discharge is 10 Amperes or less as shown by the arealabeled Townsend discharge, the voltage across the discharge variesdirectly as a function of the current such that when the voltageincreases the current increases. When the voltage is increased to apoint beyond that required to produce 10 Amperes as shown by point A,the current will then increase with a decrease in voltage therebyentering the region labeled normal glow. Point A is the tube firingpoint and upon firing of the tube the grid current will not pass beyondthe normal glow region because the grid voltage would be lowered belowthat required for maintaining the discharge between grid and cathode.Thus, it may be seen that once a sufficient voltage is applied toincrease the current along the curve to point A the current will thenrapidly increase to form a glow discharge between the grid and cathode.Some electrons from the glow discharge will move through the gridsection and be accelerated to the anode and will ionize the spacetherebetween to thereby establish cathode-to-anode conduction and firethe tube.

If the voltage between the electrodes is maintained below that requiredto produce the current at point A, this voltage being in this case byway of example, approximately l8O volts, the current will not increaseto form an arc. Thus, for example, where the grid voltage is maintainedat 178 volts above the cathode the current is on the order of i0Amperes. A positive signal voltage of 2 volts applied to the grid wouldbe sufficient to fire the tube thereby producing a circuit havingextremely great sensitivity. The point where the current begins againincreasing with an increase in voltage is the abnormal glow region shownat point B in which region greater voltages are required to producegreater conduction current. In a plasma display, the X and Y axisintersection. corresponds to theabove described electrode. I

The voltage requirement at point B is the minimum sustaining voltagerequired to maintain the discharge, and the memory margin, or inherentmemory of the plasma display is proportional to the voltage differencebetween points A and B by the relationship:

M= V V /l/2 V,,, where M is the memory margin and V, V is the bistablerange.

Referring now to F168. 4 through 8, functional equivalent circuits areillustrated which are representative of the various operating modes ofthe plasma dis play. These modes are the Erase mode, the Write mode, thepositive half cycle emitting mode, the negative half cycle emitting modeand the erased mode, wherein:

C the capacitance of the plasma C, represents the capacitance of theglass dielectric on either side of the plasma.

C, represents stray capacitance across the conductor grid lines crossingover the cell.

V the external applied cell voltage.

In accordance with Kirchoffs laws, V, C,/C,, 2C V,,.

Thus, it may be seen that the firing voltage V, which is the externallyapplied voltage just sufficient to start a sequence of discharges mustbe greater than the actual voltage required to cause these dischargessince all of this voltage does not occur across the plasma cell. Theactual external applied voltage is V,, a sustaining voltage, when theinformation is displayed but not changed and is, of course, less thanthe firing voltage but sufficient to sustain the discharge sequence.

The recurrent voltage is the magnitude of the externally applied voltageat which each discharge of a sequence of discharges is initiated and insymmetrical waveforms the recurrent voltage is the same on both positiveand negative half cycles.

The writing voltage V is the amplitude of the externally applied voltagewhen a cell is turned on, which voltage is higher than V,, while theerase voltage V, is the amplitude of an applied voltage when a cell isturned off and is less than the sustaining voltage.

The erased mode is illustrated by FIG. 5. The plasma cell is theelectrical equivalent of capacitor 50. Capacitors S2 and 54 representthe capacitance between the plasma cell and the X and Y connector linesrespectively with V, being the voltage applied on the X line and V,, thevoltage applied on the Y line. This circuit is a simple ac voltagedivider and the voltage which is developed from the ac sustainingvoltages across capacitors 52 and 54 is insufficient to ignite thecells, thus ionization does not occur. The total plate to plate voltageat any time is V, V V

In order to write, or to cause ionization across a plasma cell with theresultant glow discharge, an additional voltage must be superimposed onthe sustaining voltage such that the increased net voltage will be largeenough to ignite the cell as may be seen from the waveform of FIG. 8 andin equivalent circuit form in FIG. 6 in which the equivalent circuit forthe emitting or writing mode during the positive half cycle of thesustaining cycle is illustrated, which cycle in the upper waveform ofFIG. 8. The voltage source 60 in combination with diode 62 isrepresentative of a threshold condition above which current is allowedto flow through the light source 64 and thus generate light. Of course,light source 64 is the ionized and glowing plasma. When this happens theimpedance of the plasma cell 64 suddenly drops and the basic ac voltagedivider as shown in FIG. 5 is altered since capacitor 50 can acquire nomore voltage as the input voltage continues to rise, and as a resultcapacitances 52 and 54 acquire larger voltages than they do in theerased mode discussed with reference to FIG. 5 and the polarity of thecharge on capacitances 52 and 54 of FIG. 6 is such that they will add tothe sustaining voltage in the subsequent negative half of the sustainingvoltage cycle, thus it may be seen that the sustaining voltage alone islarge enough to reignite a plasma cell in each subsequent half cycle dueto the assistance of this additional charge on capacitances 52 and 54.

When writing, the voltage across capacitor 50 ignites the gas on thepositive sustaining cycle. From the curve of FIG. 3 it may be observedthat once in the normal glow region, this voltage is approximatelyconstant with increasing current, thus the voltage across capacitors 52and 54 increases, and V, is greater after a write pulse than after anormal sustaining pulse, the ratio of V to V, is changed and a closedcircuit after ignition results. V, is regenerated with reversed polarityeach cycle as may be seen from FIG. 7, in which the equivalent circuitfor the emitting mode during the negative half of the sustaining cycleis illustrated. This charging is identical to the emitting mode duringthe positive half cycle except that all of the polarities are reversed.Capacitors 52 and 54 are initially charged as in the positive halfcycle, with polarity reversal at the sustainer frequency. v

To selectively erase, an erase pulse is applied to the appropriate X andY lines, which pulse is smaller in amplitude than that which is used forwriting as may be seen with reference to the waveform of FIG. 8.Additionally, the Erase pulse is applied between sustain pulses; hence,the erase pulse is basically a weak sustain pulse which is large enoughto ignite the cell, which discharges the coupling capacitors in the cellwithout which reversal of polarity and charge memory is lost and thecell will not ignite in subsequent cycles unless it is again writteninto. The lost memory is of course, the lost wall charge. When erasing,the applied voltage falls below point B on the curve of FIG. 3, hencethe gas is in the Townsend discharge region and an increase in appliedvoltage increases the voltage across the equivalent capacitance 50without increasing V, across capacitors 52 and 54..Thus, the absolutevalue of V, does not increase and the next sustain pulse is insufficientwhen added to V, to fire the cell; hence, memory is lost, or erased.

It has been found that a step pulse sequence of writing and sustainingvoltage provides an improved display capability sincethe chargedeveloped on the plasma cell-walls depends on the intensity ofionization and the duration of the discharge and a rapidly increasingapplied voltage increases this intensity of ionization, and thereby thetotal created charge.

In the present embodiment, a steeply sloped writing pulse somewhat over200 volts, a sustaining voltage of approximately I40 volts and an erasepulse of approximately volts are employed during periods T, and T of theapplied waveform. These voltage requirements are obtainable because ofthe close proximity of the conductors to the glass surface of the plasmadisplays and the close spacing of opposing cell walls which is on theorder of several mills. Additionally, the particular gas compositionemployed and the pressure of the gas in Torr has a direct result uponrequiredionization voltages in accordance with the well-known Paschencurve for gases. Neon, Helium, Argon, Krypton, Xenon and Nitrogen, andmixtures of these gases maybe used to effect plasma discharge. Forexample, a Neon Nitrogen mixture with about 4 percent Nitrogen resultsin an adequate memory with sufficient visible light output. Of course,these voltages are applied negatively on the orthogonal grid with aresultant doubling of all applied voltages as is apparent from FIG. 8.

A composite equivalent circuit of the write, erase and erased modes ofFIGS. 5 through 7 is illustrated by FIG. 4. V and V,,, are selectivelyapplied with V, and Y, to the light source 64 at a polarity determinedby diodes 62 and 66 which in turn are biased by the charge on capacitors52 and 54. When the total applied voltage across light source 64 issufficient to maintain glow discharge, visible light is emanated. Ofcourse, the sustaining voltage applied via capacitors S2 and 54 willcause discharge only when the plasma is in the glow region of thedischarge curve.

Referring now to FIG. 9, a block diagram of a plasma display system isdisclosed which comprises a 256 by 256 element plasma panel whichrequires 2 N switches for each axis where N is the number ofconductivity lines per axis. Control, timing, and selection signals aregenerated at the central computer which supplies the various switchingmatrixes, Write/Erase drivers, and sustainer generators with theappropriate command logical inputs.

The X and Y axis isolation networks 70 and 72 described with referenceto FIG. 10, couple the sustaining voltage and the write or erasevoltages to the display 74 without interference with each other or withthe voltages present on other modes. The isolating network comprises amatrix of diodes and resistors which may effectively be plated directlyon the plasma panel as diode chips and film resistors with a resultantfurther reduction in circuit connection requirements.

Switchable connections in the X channel are controlled via 16 sustainswitches 76 and sixteen write switches 78 and similar switchableconnections in the Y channel are controlled via sixteen sustain switches80 and 16 write switches 82 respectively. Write and erase voltagegenerators 84 in the X channel and 86 in the Y channel supply thevoltage pulses necessary for switching and erasing to the X and Ychannels via switches 76 through 82, with timing and control coupledfrom the computer to drivers 84 and 86 and to X and Y sustainergenerators 88 and 90 respectively which may be simultaneously applied toelemental areas of the display 74 through switches 76 and 80 whileisolated from writing voltages by the isolation networks 70 and 72.Logic matrixes 92 and 94 in the X channel and 96 and 98 in the Y channelcouple element selection coding data digitally directly from thecomputer to the switching networks, and comprise a matrix arrangement ofthe switches described with reference to FIGS. 11 and 12, the interfaceportion of which is standard transistortransistor logic modulesinterfacing computer 10.

Referring now to FIG. 10, a switching and control circuit in accordancewith the present invention is shown generally at 100 which isparticularly adaptable for use with the plasma display previouslydescribed. The illustrated circuit controls the X' axis of a simple fourline plasma panel; however, any number of plasma lines may be controlledby additional connective circuitry. For a panel comprising N LINES 2 WVsustaining and writing per axis switches are required with an optimumnumber of panel elements. Thus, fora four line panel four switches areneeded, but for a 256 X 256 line panel only 64 switches are required.These switches apply simultaneously with a control voltage and sustainervoltage without interference, one with the other, the control voltages,being, of course, the write and erase voltages required by the glowareas.

Selection of the glow discharge points for writing or erasing isaccomplished by steering voltage pulses generated in a Write/Erasedriver 116 to which panel lines A, B, C and D which are illustrated asnodes 104 through 110, to which the X axis lines are coupled, thevoltages on which, oppositively to the voltage counterparts on the Yaxis (not shown) causes the plasma elements which are bistable devices,either on or off to glow or not glow. The write and erase signals areapplied to the Write/Erase driver 116 in digital form directly from thecomputer.

Two types of switches are required, write switches and sustain switches.The function of the write switches 102A and 1023 is to apply a writingvoltage to the panel lines 104 through which panel lines are alsoconnected to separate sustaining switches 112A and 1 128. The functionof the sustaining switches is to provide a path back to the sustainingvoltage generator 1 14 for all but one of the panel lines in a group ofpanel lines such as 104 and 106 or 108 and 110. [n this way only onepanel line will receive a writing voltage from driver 116, while all ofthe other lines can simultaneously be sustained. With a 50 KC pulsetrain, writing will occur every 20 p. sec. The writing and sustainingswitches are the element switches such as transistor switches.

Each write switch couples the writing voltage to a different group ofpanel lines, switch 102 to elements 104 and 106 and other switch 102 toelements 108 and 1 10. The sustaining switches 112A and 112B couple outany panel lines from the write voltage to which writing volt ages is notintended. All other lines are coupled back to the sustainer voltagegenerator 114.

A diode resistor network comprising diode and resistor 122 associatedwith panel line 104, diode 124 and resistor 126 associated with panelline 106, diode 128 and resistor 130 associated with panel line 108 anddiode 132 and resistor 134 associated with panel line 110 isolate thewrite voltage from the sustainer voltage such that writing andsustaining to different panel lines may occur simultaneously and glowingand sustained plasma areas will not dim while writing occurs at otherpanel points. Diode and resistive isolation network 120 through 134 maycomprise diode chips and film resistors of well-known and conventionaldesign, or may comprise switches such as two point diode switches.

Before writing, the write switches are open. When writing, the writeswitch associated with the selected panel line is closed, and a writepulse is applied to that line. For example, if it is desired to writeinto line 104, switch 102A is closed. The sustain switches are normallyclosed; however, when writing, a switch is opened. For the casedescribed above, switch 112A is opened and the voltage applied to line106 is conducted through closed switch 1 128 on the positive half cycleback to the sustainer generator 114. 7

During the negative portion of the sustainer waveform, the negative edgeswitch connects point T to point R thereby providing an unblocked pathfor the negative half cycle of the sustainer. Negative edge switch 140senses when the sustainer is going negative as described with referenceto FIG. 13. This is necessary because writing occurs only on thepositive half cycle; hence, the separate and noninterfering negativesustaining path. During the negative half cycle, diodes 142 and 144block the sustainer from the panel lines, and the alternate pathprovided at T allows the sustainer to reach these points, and diodes 146and 148 block on the positive half cycle with current flow throughdiodes 142 and 144. When writing, the voltage at points M and N is morepositive than the sustainer voltage, and the polarity of diodes 146 and148 will not block this voltage, since their function is only to gatethe negative sustainer to nodes A and B; hence, the alternate path.

The quantity of circuits is minimized by the matrix arrangement employedin the present invention. The base emitter of each transistor switch isconnected to each other transistor switch in a diode matrix form. Boththe base and emitter lines of the simple transistor current switchesemployed in switches 102 and 112 share a common physical location, thuscommon mode rejection of ground noise between the low level logic andthe high level drive electronics without the need for expensive linereceivers and line drivers is provided.

Referring now to FIG. 11, a sustainer switch circuit is shown generallyat 160. The base emitter portion of driver transistor 162 is connectedin matrix arrangement to conventional transistor transistor logicmodules, thus conserving components and serving the address decodingfunctions. Input current is coupled through resistors 164 and 166 toswitching transistor 168 which opens and closes to provide a sustainercurrent path in accordance with the input control from the centralcomputer.

Referring now to FIG. 12, a Write/Erase switch circuit is showngenerally at 170. The base emitter portion of transistor 172 isconnected in matrix arrangement to conventional transistor transistorlogic modules in a similar manner to the matrix arrangement of thesustainer switches described with reference to FIG. 11. Input current iscoupled through resistor 174 to transistor switch 176 which acts tocouple the Write/Erase driver output through the switch to the isolationnetwork in accordance with the input control from the central computervia the logic matrix. Both writing and erasing pulses are selectivelycoupled through transis tor 176, as these are merely time displacedvoltage pulses of different magnitudes.

Referring now to FIG. 13, a circuit diagram of the sustainer generatorand negative edge switch is illustrated generally at 200. The outputlevel control circuit 202 comprises three transistor switches, 204, 206and 208, which generate the voltages necessary to form the sustainerwaveform shown in FIG. 9. A clock pulse of 50 KC is supplied to the baseof transistor switch 204 which short circuits the applied voltage toground during the zero voltage portion of the sustainer waveform.

As described with reference to FIG. 8, the erase pulse of 125 voltsprovides a selective erase of the display; that is, one spot at a timeis erased every microseconds at 50 KC when erasure of selected areas isdesired; however, a reset, or simultaneous erasure capability of all ofthe plasma cells, is provided by switch 206, which when actuated by thereset pulse provides a voltage drop across zener diode 210 sufficient tocouple the erase voltage of 125 volts onto the sustainer line. Thisvoltage will not cause the capacitance (from plasma to glass) to chargeon the next occurring cycle, hence, erasure occurs in 20 microseconds.The sustainer switches are not reset, and the sustainer level is reducedto the erase level of 125 volts during the sustaining portion of thecycle, T

Switch 208 is supplied via the logic matrix from the central computerwith a dc pulse to couple 70 volts to the sustainer line during the Tportion of the cycle and a drop across zener diode 212 sufficient toresult in a 70-volt output is effected.

The varying output of the level control circuit 202 is supplied to theoutput drive circuit 220 which comprises two complimentary Darlingtoncurrent amplifers 222 and 224 the former comprising NPN transistors andthe latter comprising PNP transistors, with amplifier 222 driving theload in the positive direction and amplifier 224 driving the load in thenegative direction. Biasing potentials of 140 and 200 volts are providedfrom external power supplies. Thus, current multiplication is providedfor driving a low impedance output from a high impedance input withcurrent gain, but no voltage gain. Diode 226 provides a conduction pathfrom the isolation resistors for increased stability. The output on line228 is the sustainer voltage.

The negative edge switch 230 transfers the negative portion of thesustaining voltage from line 228 to line 232 during that portion of thewaveform when it is changing in the negative direction. When point Rgoes negative, capacitor 234 charges through the baseemitter junction ofswitching transistors 236 and 238 thereby turning transistors 236 and238 ON which closes the switch. Suitable emitter-to-base biasing isprovided by resistors 240 and 242 for transistors 236 and 238respectively.

Referring now to FIG. 14, the Write/Erase driver circuit is showngenerally at 250. The generated writing pulse of 200 volts is derivedfrom an external supply, not shown, and is coupled to the write switchesduring a portion of the T, positive half cycle of the sustainer by atransistor switch 252 which is driven by a driver transistor 254. Asuitable control pulse is applied to the base of transistor 254 from thecentral computer via coupling capacitor 256. Resistors 258, 260 and 262provide suitable biasing for transistors 252 and 254, respectively.

The generated erase pulse of volts is similarly derived from an externalsupply, not shown, and is coupled to the Write/Erase switches during aportion of the T sustainer cycle by a transistor switch 264 which isdriven by a driver transistor 266. While T, is approximately 5 to 8microseconds and the time between pulses T is also from 5 to 8microseconds, other timing sequences and voltage levels may be employeddepending upon the particular characteristics of the plasma drive used.The erase pulse is advantageously of approximately 23 microsecondsduration. A suitable control pulse is applied to the base of transistor266 from the central computer via coupling capacitor 268. Resistors 268,270 and 272 provide biasing for transistors 264 and 266, respectively.

Referring now to FIG. 15, the X channel connections for a 64 line plasmadisplay are illustrated. The glass plasma panel shown generally at 302has plated thereon a plurality of integrated circuit chips 304 through3l8which comprise the resistor-diode insulation circuitry described withreference to FIG. 10 for a four line system. FIG. 15 illustrates thereduction in external connections to the plasma panel required by thepresent system, with all writing, sustaining and erasing voltages beingreceived by 16 lines rather than by 128 lines as in the prior art. Thealternating I40 volt sustainer voltage is applied to lines X1 throughX64 via eight sustainer switches S through S each of which switchescouples the sustainer voltage to eight lines.

As described with respect to FIG. 10, when no writing or erasingvoltages are applied, lines 320 through 334 couple the volt sustainer tothe isolation circuits 304 through 318, respectively. When writingpulses are selectively applied. via the Write/Erase switches W through Wto lines 320 through 334, respectively, writing or erasing isaccomplished. For example, to write on line X,, a writing pulse isapplied through switch W, via line 320 to the isolation network 304.With a writing pulse of 200 volts, this voltage is coupled via resistor336 to line X which is connected between resistor 336 and diode 338 toprovide a direct path for the writing voltage to line X Sustainer switchS is open while switches S through S are closed, thereby shorting linesX through X back to the sustainer generator at l40 volts, leaving 200volts on line X. only. The back biasing of diode 338 provides isolationof the 140 volts sustainer from the 200 volt writing pulse. A similar200 volt writing pulse is, of course, applied to the corresponding Yline (not shown) when writing is effected, the connections for Y throughY being identical to those for X through X with a waveformcorrespondence as illustrated by FIG. 8.

Referring now to FIG. 16, the X and Y grid matrix for a four line plasmapanel, the X axis of which is described with reference to FIG. 10, isshown generally at 350. Lines 1 through 4 of the X matrix are plated ona glass substrate 30, and the corresponding Y axis lines 1 through 4 areplated on a glass substrate 32 which is isometrically illustrated inFIG. 2. The X and Y isolation networks 352 and 354 are also plated onglass substrates 30 and 32, respectively, and all the circuitconnections required to the panel, 2 VIV, where N is the number of panellines per axis, are shown as points 356, 358, 360 and 362 for the X axisgrid and 364, 366, 368 and 370 for the Y axis grid. It may be observedthat the X and Y axis circuitry is identical and that whatever voltageis applied positively on the X axis grid is also applied negatively onthe Y axis grid, thereby producing a composite absolute voltage betweenthe X and Y axis grids of twice any individually applied voltage to anyone line in either the X or Y axis grids as may be observed withreference to FIG. 8, in which the absolute values of the write and erasepulsesare 400 volts and 250 volts, respectively, with an absolutesustainer voltage of 280 volts.

As described with reference to FIG. 10, writing and erasing voltages arecoupled from the Write/Erase switches to the isolation network 352 forthe X axis via lines 372 and 374, and the sustainer voltage is coupledto the isolation network 352 from the X axis sustainer switches vialines 376 and 378. In a similar manner, the writing and erasing voltagesare coupled to the Y axis isolation network 354 from the Y Write/Eraseswitches via lines 380 and 382, and the Y axis sustainer voltage iscoupled to isolation network 354 from the Y axis sustainer switches vialines 384 and 386.

The plasma between glass plates 30 and 32 is ionized by the voltagedeveloped between the X and Y axis grid spaced intersection points byvirtue of the voltage capacitively built up therebetween and theresultant dis charge through the plasma as previously described. Ofcourse, this simplified plasma panel of four lines by four lines isillustrative only and in practice, a 256 by 256 line matrix ispreferably employed.

While particular embodiments of the invention have been shown anddescribed, various modifications thereof will be apparent to thoseskilled in the art. For example, the circuitry of the present inventionmay be effectively employed in displays of the electroluminescent type,the light emitting diode matrix type and in displays in which thereflectivity of a surface is controlled. Therefore, it is not intendedthat the invention be limited to the disclosed embodiments or detailsthereof and departures may be made therefrom within the spirit and scopeof the invention as defined in the appended claims.

What is claimed is:

l. A visual display system in which a plurality of illuminated areas arecreated by the crossing of wire grids comprising:

switching means for controlling the generated dissustaining means formaintaining the display once generated;

means for isolating said sustaining means from said switching means suchthat sustaining occurs independently of signals switched by saidswitching means;

writing means for generating a voltage sufficient to cause illuminationof selected areas of said display, said writing voltage being greaterthan said sustaining voltage; and

means included in said switching means for enabling the simultaneousapplication of said writing voltage sequentially to selected crossingsof said wire grid while sustaining voltage is applied to other crossingsof said wire grid;

said sustaining voltage and said writing voltage being isolated one fromthe other.

2. A visual display system in accordance with claim 1 wherein each ofsaid switching means is coupled to a plurality of wires of said grid andwherein the number of said switching means is less than the number ofintersections of said wire grids.

3. A visual display system in accordance with claim 2 wherein said wiregrids intersect at N points and wherein the number of control swit chesrequired for said N points is substantially 4 Vfi.

4. A visual display system in accordance with claim 3 wherein saidsustaining voltage and said writing voltage are alternating voltages.

5. A visual display system in accordance with claim 3 wherein saidsustaining voltage and said writing voltage are pulsed dc voltages.

6. A visual display system in accordance with claim 3 wherein saiddisplay is of the capacitively coupled type wherein said wire grids areon opposite sides of an illuminatable substance and cause a capacitivedischarge at selective locations through said illuminat'able substance.

7. A visual display system in accordance with claim 6 furthercomprising;

means for generating an erasing voltage for selectively erasing portionsof said visual display wherein said erasing voltage is applied throughthe same switches through which said writing voltage is applied to saiddisplay.

8. A visual display system in accordance with claim 7 wherein themagnitude of said erasing voltage is less than the magnitude of saidwriting voltage and more than the magnitude of said sustaining voltage.

9. A capacitively coupled plasma display system of the type in which twowire grids are plated on the surfaces of two dielectrics and areseparated from each other by a fixed distance with an ionizable gastherebetween comprising:

writing means for generating a voltage sufiiciently high to causeionization with resultant glow discharge of said ionizable gas;

sustaining means for generating a voltage sufficiently high to maintainsaid glow discharge once initiated by said writing voltage;

means for noninductively coupling said writing voltage and saidsustaining voltage to selected areas of said plasma display inaccordance with matrix selection data from said first mentioned means inboth an X channel and a Y channel;

said X channel corresponding to one of said conductive grids and said Ychannel corresponding to the other of said conductive grids;

said X grid and said Y grid crossing in matrix form;

means coupled to said switching means for isolating said writing voltageand said sustaining voltage one from the other prior to coupling to saidconductive grid networks;

the source of said matrix selection data comprising a digital computer;and

said isolation network comprising a plurality of diode and resistivenetworks for cyclically coupling said writing and sustaining voltages tocertain of said plasma areas while simultaneously blocking said writingvoltage from other of said plasma areas.

10. The combination of claim 9 further comprising:

means for noninductively controlling said writing voltage with saidsustaining voltage such that said writing voltage is selectively appliedto areas of said visual display to produce visual indication at saidareas without loss of said sustaining voltage at areas of said visualdisplay at which said writing voltage is not applied.

11. A visual display system in accordance with claim 10 wherein saidmeans for controlling includes;

means for isolating said sustaining voltage from said writing voltage.

12. A visual display system in accordance with claim 11 wherein saidwriting voltage are alternating signals.

13. In combination:

first and second sets of conductors;

means for producing light at a plurality of locations, said locationsbeing situated at intersections of conductors of said first set ofconductors with conductors of said second set of conductors;

a first set of diodes, said first set of diodes being coupled to saidconductors of said first and second sets of conductors;

a plurality of switch means coupled to said first set of diodes forcontrolling which of said light producing means produce light;

means for generating a sustaining voltage; and

a second set of diodes, said second set of diodes being coupled to saidsustaining voltage generating means and to said first and second sets ofconductors.

14. The combination of claim 13 wherein said switch means are less innumber than the total number of conductors of said first and second setsof conductors.

15. The combination of claim 14 wherein the number of said switch meansper set of conductors is substantially two times the square root of thenumber of conductors in said set of conductors.

16. A computer controlled display device comprising in combination:

an array of crosspoint cells defined by respective row and columnconductors;

a source of alternating polarity sustaining signals;

a plurality of diodes, said diodes having first and second terminals,said first terminals of each of said diodes being coupled to separateones of said row and column conductors;

a plurality of first switch means, said first switch means being coupledto said second terminals of said diodes, said switch means conductingwhen data displayed on said display device is being sustained;

a source of writing signals, said writing signals causing selected onesof said crosspoint cells to emit light when said writing signals arecoupled to selected ones of said row and'column conductors;

a plurality of second switch means, said second switch means couplingsaid writing signals to selected ones of said row and column conductorswhen said second switch means are conducting; and

means for operating said first and second switch means in response tosignals from said computer.

17. The combination of claim 16 wherein said array of crosspoint cellscomprises a plasma display panel.

18. The combination of claim 17 further comprising a plurality ofresistors, one of said resistors being connected between each of saidsecond terminals of said diodes and said first switch means.

2. A visual display system in accordance with claim 1 wherein each ofsaid switching means is coupled to a plurality of wires of said grid andwherein the number of said switching means is less than the number ofintersections of said wire grids.
 3. A visual display system inaccordance with claim 2 wherein said wire grids intersect at N2 pointsand wherein the number of control switches required for said N2 pointsis substantially 4 Square Root N.
 4. A visual display system inaccordance with claim 3 wherein said sustaining voltage and said writingvoltage are alternating voltages.
 5. A visual display system inaccordance with claim 3 wherein said sustaining voltage and said writingvoltage are pulsed dc voltages.
 6. A visual display system in accordancewith claim 3 wherein said display is of the capacitively coupled typewherein said wire grids are on opposite sides of an illuminatablesubstance and cause a capacitive discharge at selective locationsthrough said illuminatable substance.
 7. A visual display system inaccordance with claim 6 further comprising; means for generating anerasing voltage for selectively erasing portions of said visual displaywherein said erasing voltage is applied through the same switchesthrough which said writing voltage is applied to said display.
 8. Avisual display system in accordance with claim 7 wherein the magnitudeof said erasing voltage is less than the magnitude of said writingvoltage and more than the magnitude of said sustaining voltage.
 9. Acapacitively coupled plasma display system of the type in which two wiregrids are plated on the surfaces of two dielectrics and are separatedfrom each other by a fixed distance with an ionizable gas therebetweencomprising: writing means for generating a voltage sufficiently high tocause ionization with resultant glow discharge of said ionizable gas;sustaining means for generating a voltage sufficiently high to maintainsaid glow discharge once initiated by said writing voltage; means fornoninductively coupling said writing voltage and said sustaining voltageto selected areas of said plasma display in accordance with matrixselection data from said first mentioned means in both an X channel anda Y channel; said X channel corresponding to one of said conductivegrids and said Y channel corresponding to the other of said conductivegrids; said X grid and said Y grid crossing in matrix form; meanscoupled to said switching means for isolating said writing voltage andsaid sustaining voltage one from the other prior to coupling to saidconductive grid networks; the source of said matrix selection datacomprising a digital computer; and said isolation network comprising aplurality of diode and resistive networks for cyclically coupling saidwriting and sustaining voltages to certain of said plasma areas whilesimultaneously blocking said writing voltage from other of said plasmaareas.
 10. The combination of claim 9 further comprising: means fornoninductively controlling said writing voltage with said sustainingvoltage such that said writing voltage is selectively applied to areasof said visual display to produce visual indication at said areaswithout loss of said sustaining voltage at areas of said visual displayat which said writing voltage is not applied.
 11. A visual displaysystem in accordance with claim 10 wherein said means for controllingincludes; means for isolating said sustaining voltage from said writingvoltage.
 12. A visual display system in accordance with claim 11 whereinsaid writing voltage are alternating signals.
 13. In combination: firstand second sets of conductors; means for producing light at a pluralityof locations, said locations being situated at intersections ofconductors of said first set of conductors with conductors of saidsecond set of conductors; a first set of diodes, said first set ofdiodes being coupled to said conductors of said first and second sets ofconductors; a plurality of switch means coupled to said first set ofdiodes for controlling which of said light producing means producelight; means for generating a sustaining voltage; and a second set ofdiodes, said second set of diodes being coupled to said sustainingvoltage generating means and to said first and second sets ofconductors.
 14. The combination of claim 13 wherein said switch meansare less in number than the total number of conductors of said first andsecond sets of conductors.
 15. The combination of claim 14 wherein thenumber of said switch means per set of conductors is substantially twotimes the square root of the number of conductors in said set ofconductors.
 16. A computer controlled display device comprising incombination: an array of crosspoint cells defined by respective row andcolumn conductors; a source of alternating polarity sustaining signals;a plurality of diodes, said diodes having first and second terminals,said first terminals of each of said diodes being coupled to separateones of said row and column conductors; a plurality of first switchmeans, said first switch means being coupled to said second terminals ofsaid diodes, said switch means conducting when data displayed on saiddisplay device is being sustained; a source of writing signals, saidwriting signals causing selected ones of said crosspoint cells to emitlight when said writing signals are coupled to selected ones of said rowand column conductors; a plurality of second switch means, said secondswitch means coupling said writing signals to selected ones of said rowand column conductors when said second switch means are conducting; andmeans for operating said first and second switch means in response tosignals from said computer.
 17. The combination of claim 16 wherein saidarray of crosspoint cells comprises a plasma display panel.
 18. Thecombination of claim 17 further comprising a plurality of resistors, oneof said resistors being connected between each of said second terminalsof said diodes and said first switch means.